1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. More particularly, the present invention relates to a resistance load type Static Random Access Memory (SRAM) in which a resistance pattern and a power supply line pattern are formed in a same layer, and a manufacturing method of the resistance load type SRAM.
2. Description of the Related Art
In recent years, in an SRAM, high integration has been carried out. As an SRAM suitable for the high integration, a resistance load type SRAM is conventionally known. A 1-bit memory cell of the resistance load type SRAM is composed of four N-type metal-oxide-semiconductor (MOS) transistors T1 to T4 and two load resistive elements R1 and R2 of high resistance, as in an equivalent circuit shown in FIG. 16.
As shown in FIG. 16, the drain of each of the driving MOS transistors T1 and T2 of a pair is connected to the gate of the other of the MOS transistors T1 and T2. Also, both of drains of the driving MOS transistors T1 and T2 as accumulation nodes N1 and N2 are connected to a power supply line Vcc through the load resistors R1 and R2, respectively. Also, both of the sources of the driving MOS transistors T1 and T2 are connected in common to a ground potential line Vss. The driving MOS transistors T1 and T2 and the load resistors R1 and R2 construct a flip-flop circuit and a small amount of current is supplied from a power supply. One of the source and drain regions of each of the data transfer MOS transistors T3 and T4 is connected to a corresponding one of the accumulation nodes N1 and N2 of the flip-flop circuit. Also, the other of the source and drain regions of each of the MOS transistors T3 and T4 is connected to a corresponding one of digit lines D1 and D2. Both of the gate electrodes of the MOS transistors T3 and T4 are connected to a word line W.
Next, a first structure example of a memory cell in the conventional resistance load type SRAM will be described with reference to FIGS. 1A, 1B, 2A and 2B.
FIG. 1A is a plan view illustrating a lower layer plane structure in the first structure example of the memory cell of the conventional resistance load type SRAM, and FIG. 1B is a plan view illustrating an upper layer plane structure of the conventional first structure example of the memory cell. Also, FIG. 2A is a cross sectional view of the first structure example of the memory cell along the 2A-2A' line shown in FIGS. 1A and 1B, and FIG. 2B is a cross sectional view of the first structure example of the memory cell along the 2B-2B' line shown in FIG. 1A and 1B.
As shown in FIGS. 1A, 1B, 2A and 2B, an element isolation region 2, a gate oxide film 3 and a gate polycide layer 4 are formed in the surface of a silicon substrate 1. The gate polycide layer 4 is formed as a lamination layer of a polysilicon layer and a silicide layer on the polysilicon layer. Source and drain diffusion layers are formed on the surface of the silicon substrate 1 on both sides of the gate polycide layer 4. These MOS transistors correspond to the MOS transistors T1 to T4 shown in FIG. 16, respectively. In this case, the gate polycide layer 4 as the gate electrodes of the MOS transistors T3 and T4 is also used as the word line W shown in FIG. 16.
An interlayer insulating film 5 is laminated on the MOS transistors T1 to T4, and a polysilicon layer 6 is formed and patterned on the interlayer insulating film 5 to form polysilicon patterns 6a and 6b. The polysilicon patterns 6a are doped with phosphorus ions to form low resistance sections, and act as power supply line patterns. Also, the polysilicon patterns 6b are left in a high resistance state. These high resistance sections correspond to the load resistors R1 and R2 shown in FIG. 16, respectively.
An interlayer insulating layer 7 is formed on the polysilicon layer 6, and a metal layer is formed on the interlayer insulating film 7, and then the metal layer is patterned to form ground line patterns 8.
Further, an interlayer insulating film 9 is formed on the interlayer insulating film 7 and the ground line patterns B. A metal layer is formed on the interlayer insulating film 9, and then the metal layer is patterned. These metal layers 10 correspond to the digit line D1 and D2 shown in FIG. 16, respectively.
In this case, the polysilicon layer 6b, the gate polycide layer 4 and the silicon substrate 1 are connected by a common contact 11. Also, the metal layer 8 as the ground line patterns and the silicon substrate 1 are connected by ground contacts 12. Further, the metal layers 10 as the digit lines D1 and D2 and the silicon substrate 1 are connected by digit contacts 13.
In the memory cell of the first structure example described above, there is a problem that a short-circuit is easily formed between the ground contact 12 and the polysilicon layer 6b or the gate polycide layer 4. The reason will be described below.
As shown in FIG. 2A, the ground contact 12 must be formed on the silicon substrate 1 between a gate polycide layer 4a and a gate polycide layer 4b such that the ground contact 12 and one of the gate polycide layers 4a and 4b do not form a short-circuit. For its purpose, when a hole for the ground contact 12 is formed, the position of the ground contact 12 must be adjusted in such a manner that it is not displaced with respect to the patterns of the gate polycide layers 4.
However, the ground contact 12 must be formed between the polysilicon layers 6a and 6b formed in the upper layer of the gate polycide layers 4. Therefore, the position of the ground contact 12 must be also adjusted in such a manner that it is not displaced with respect to the polysilicon layers 6a and 6b.
Generally, in the step that the layout of a memory cell is designed, the polysilicon layers 6b are designed to be formed on the positions straightly above the gate polycide layers 4a and 4b. Therefore, if the ground contact 12 is formed in such a manner that a short-circuit is not formed between the ground contact 12 and each of the gate polycide layers 4a and 4b, the short-circuit would not be formed between the ground contact 12 and each of the polysilicon layers 6b.
In actual, however, because a patterning process of the gate polycide layer 4 and a patterning process of the polysilicon layer 6 are separately performed in the manufacturing step, both of the gate polycide layers 4a and 4b and the polysilicon layers 6b are never completely coincident with each other. Thus, there is a slight position displacement between these two patterns.
For this reason, when the hole for the ground contact 12 is formed, if the position of the ground contact 12 is adjusted to be suitable for the gate polycide layers 4a and 4b, a short-circuit becomes easy to be formed between the ground contact 12 and the polysilicon layers 6b. On the other hand, when the position of the ground contact 12 is adjusted to be suitable for the polysilicon layers 6b, a short-circuit becomes easy to be formed between the ground contact 12 and the gate polycide layers 4a and 4b.
A second structure example of a memory cell formed to solve the above problem is disclosed in Japanese Laid Open Patent Disclosure (JP-A-Heisei 3-248558). Hereinafter, the second structure example of a memory cell of a conventional resistance load type SRAM mentioned in the above reference will be described with reference to FIGS. 3A, 3B, 4A and 4B.
FIG. 3A is a plan view illustrating the lower layer plane structure of a memory cell in the second structure example of a memory cell of conventional resistance load type SRAM, and FIG. 3B is a plan view illustrating the upper layer plane structure of the memory cell. Also, FIG. 4A is a cross sectional view in the second structure example of the memory cell along the 4A-4A' line in FIGS. 3A and 3B, and FIG. 4B is a cross sectional view in the second structure example of the memory cell along the 4B-4B' line in FIGS. 3A and 3B.
As shown in FIGS. 3A and 3B and FIGS. 4A and 4B, an element isolation region 22 is formed in the surface of a silicon substrate 21. Further, a gate lamination film composed of a gate oxide film 23, a gate polycide layer 24, a first silicon oxide film 25, a polysilicon layer 26, and a second silicon oxide film 27 is formed. Then, the gate lamination film is patterned to form gate lamination film patterns 28. Source and drain diffusion layers are formed on the surface of the silicon substrate 21 on both sides of each of the gate lamination film patterns 28. These correspond to the MOS transistors T1 to T4 shown in FIG. 16, respectively.
In this case, the gate polycide layers 24 as the gate electrode of the MOS transistors T3 and T4 are also used as the word line W shown in FIG. 16. The polysilicon layer 26 of the gate lamination film pattern 28 acts as a load resistor and corresponds to the load resistor R1 or R2 shown in FIG. 16.
Also, as shown in FIG. 4B, in a portion 28a of the gate lamination film pattern 28 which corresponds to the gate electrode of one of the driving MOS transistors T1 and T2 shown in FIG. 16, a portion of the gate oxide film pattern 23 and a portion of the first silicon oxide film pattern 25 are previously removed so as to electrically connect the gate polycide layer 24 as the gate electrode and the polysilicon layer 26 as the load resistor to the drain diffusion layer of the other driving MOS transistors.
An interlayer insulating film 29 is laminated on these MOS transistors T1 to T4, and power supply line patterns 30 and ground line patterns 31 are formed on the interlayer insulating film 29. The power supply line pattern 30 and the polysilicon layer 26 are connected by a power supply contact 32. Also, the ground line pattern 31 and the silicon substrate 21 are connected by a ground contact 33. Further, an interlayer insulating film 34 is formed on the interlayer insulating film 29, the power supply line patterns 30 and the ground line patterns 31. Then, a metal layer is formed on the interlayer insulating film 34 and is patterned. The patterns 35 correspond to the digit lines D1 and D2 shown in FIG. 16, respectively. In this case, the metal layers 35 as the digit lines D1 and D2 and the silicon substrate 21 are connected by digit contacts 36.
In the memory cell of the second structure example described above, the polysilicon layer 26 and the gate polycide layer 24 as the load resistors are laminated and are patterned at the same time to form the gate lamination film pattern 28. Therefore, if a position adjustment is performed with respect to the gate lamination film pattern 28 when a hole for the ground contact 33 is formed, the ground contact 33 can be formed in such a manner that a short-circuit is not formed to neither in the polysilicon layer 26 nor in the gate polycide layer 24 as the load resistor.
By the way, in the second structure example of the memory cell of the conventional resistance load type SRAM described above, the polysilicon layer 26 as the load resistor and the power supply line pattern 30 are connected by the power supply contact 32. A contact forming area 37 in which the power supply contact 32 is formed needs to be previously provided for the gate lamination film pattern 28 as the gate electrode of each of the driving MOS transistors T1 and T2 as shown in FIG. 3A. Therefore, there is a problem in increase of the area of the memory cell. In this manner, the SRAM can not be highly integrated.
Also, there is a case that the hole for the power supply contact 32 is formed to have a slight displacement in the adjustment, and the power supply contact 32 is formed out of the contact forming area 37. In this case, a portion of the power supply contact 32 is formed on the side of the gate lamination film pattern 28. Thus, because the gate polycide layer 24 and the power supply contact 32 are electrically connected by the power supply contact 32, there is a problem that the memory cell does not operate in a normal state.
In this manner, because the mask positioning margin in the manufacture process is small, there is a problem of low productivity.